327,41 €
363,79 €
-10% with code: EXTRA
Ultra-Low Energy Domain-Specific Instruction-Set Processors
Ultra-Low Energy Domain-Specific Instruction-Set Processors
327,41
363,79 €
  • We will send in 10–14 business days.
1. General overview and context2. Global state-of-the-art overview 3. Energy consumption breakdown for embedded platform targets 4. High level embedded arch and compiler requirements 5. Overall architecture exploration framework 6. Clustered loop buffer and data cluster organisation 7. Multi-threading in uni-threaded processors8. Indirectly addressed arrays and dynamic data structure handling on scratchpad memories 9. Asymmetric foreground memory organisation 10. Exploiting word-width informati…
363.79
  • Publisher:
  • ISBN-10: 9048195276
  • ISBN-13: 9789048195275
  • Format: 15.6 x 23.4 x 2.4 cm, kieti viršeliai
  • Language: English
  • SAVE -10% with code: EXTRA

Ultra-Low Energy Domain-Specific Instruction-Set Processors (e-book) (used book) | bookbook.eu

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1. General overview and context

2. Global state-of-the-art overview

3. Energy consumption breakdown for embedded platform targets

4. High level embedded arch and compiler requirements

5. Overall architecture exploration framework

6. Clustered loop buffer and data cluster organisation

7. Multi-threading in uni-threaded processors

8. Indirectly addressed arrays and dynamic data structure handling on scratchpad memories

9. Asymmetric foreground memory organisation

10. Exploiting word-width information in the processor datapath

11. Advanced strength reduction in shift-add based operations

12. Bioimaging application demonstrator

EXTRA 10 % discount with code: EXTRA

327,41
363,79 €
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  • Author: Francky Catthoor
  • Publisher:
  • ISBN-10: 9048195276
  • ISBN-13: 9789048195275
  • Format: 15.6 x 23.4 x 2.4 cm, kieti viršeliai
  • Language: English English

1. General overview and context

2. Global state-of-the-art overview

3. Energy consumption breakdown for embedded platform targets

4. High level embedded arch and compiler requirements

5. Overall architecture exploration framework

6. Clustered loop buffer and data cluster organisation

7. Multi-threading in uni-threaded processors

8. Indirectly addressed arrays and dynamic data structure handling on scratchpad memories

9. Asymmetric foreground memory organisation

10. Exploiting word-width information in the processor datapath

11. Advanced strength reduction in shift-add based operations

12. Bioimaging application demonstrator

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