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Description
Chemical Mechanical Planarization (CMP) is one of the key enabling technologies for modern IC fabrication. However, mainly due to the high complexities coming from various interactions among mechanical reactions and chemical reactions, its fundamental working mechanism is still not fully understood. This book summarizes key CMP applications and challenges in modern IC fabrication, and provides a comprehensive physical CMP process model that can be applied for process characterization, process opti-mization, consumable development, and layout design for manufac-turing (DFM). The model has been built from an abrasive scale to a chip scale, focusing on practical application for DFM while also consi-dering CMP process conditions as key input parameters. Also included are examples of a computer model application for pattern dependent variation in shallow trench isolation CMP and the model verification with specially designed test chip. The model should help CMP pro-fessionals, DFM engineers and students of IC fabrication obtain a fun-damental understanding of CMP process and characterize and im-prove a process through real application.
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Chemical Mechanical Planarization (CMP) is one of the key enabling technologies for modern IC fabrication. However, mainly due to the high complexities coming from various interactions among mechanical reactions and chemical reactions, its fundamental working mechanism is still not fully understood. This book summarizes key CMP applications and challenges in modern IC fabrication, and provides a comprehensive physical CMP process model that can be applied for process characterization, process opti-mization, consumable development, and layout design for manufac-turing (DFM). The model has been built from an abrasive scale to a chip scale, focusing on practical application for DFM while also consi-dering CMP process conditions as key input parameters. Also included are examples of a computer model application for pattern dependent variation in shallow trench isolation CMP and the model verification with specially designed test chip. The model should help CMP pro-fessionals, DFM engineers and students of IC fabrication obtain a fun-damental understanding of CMP process and characterize and im-prove a process through real application.
Reviews