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- Author: Sadiq M Sait
- Publisher: VDM Verlag
- ISBN-10: 363905525X
- ISBN-13: 9783639055252
- Format: 15.2 x 22.9 x 0.7 cm, minkšti viršeliai
- Language: English
- SAVE -10% with code: EXTRA
Parallel Inverse Halftoning via Look-Up Table (LUT) Partitioning (e-book) (used book) | bookbook.eu
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The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this book we propose six algorithms to parallelize the LUT method so that more pixels can be concurrently inverse halftone using minimum additional hardware. The proposed algorithms partition the single LUT of serial LUT method into N smaller Look-Up Tables (s- LUTs) such that the total number of contents in all s-LUTs remain equal to the number of contents in the single LUT of serial LUT method. The proposed parallel algorithms have image quality equal to the serial LUT method when gain in clock cycles over the serial method is less and have lesser image quality comparetively to serial LUT method when gain in clock cycles over the serial method is very high. The parallel algorithms can be implemented on FPGA (Field Programmable Gate Arrays) devices with external CAM (Content Addressable Memories) and ROM (Read Only Memories)
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- Author: Sadiq M Sait
- Publisher: VDM Verlag
- ISBN-10: 363905525X
- ISBN-13: 9783639055252
- Format: 15.2 x 22.9 x 0.7 cm, minkšti viršeliai
- Language: English English
The Look-Up Table (LUT) method for inverse halftoning is fast and computation-free technique employed to obtain good quality images. In this book we propose six algorithms to parallelize the LUT method so that more pixels can be concurrently inverse halftone using minimum additional hardware. The proposed algorithms partition the single LUT of serial LUT method into N smaller Look-Up Tables (s- LUTs) such that the total number of contents in all s-LUTs remain equal to the number of contents in the single LUT of serial LUT method. The proposed parallel algorithms have image quality equal to the serial LUT method when gain in clock cycles over the serial method is less and have lesser image quality comparetively to serial LUT method when gain in clock cycles over the serial method is very high. The parallel algorithms can be implemented on FPGA (Field Programmable Gate Arrays) devices with external CAM (Content Addressable Memories) and ROM (Read Only Memories)
Reviews