- We will send in 10–14 business days.
/images/books/13174706/9783639098594.jpg)
- Author: Zhiyi Yu
- Publisher: VDM Verlag
- ISBN-10: 3639098595
- ISBN-13: 9783639098594
- Format: 15.2 x 22.9 x 0.9 cm, softcover
- Language: English
- SAVE -10% with code: EXTRA
High Performance and Energy Efficient Many-core DSP Systems An Asynchronous Array of Simple Processors (e-book) (used book) | bookbook.eu
Reviews
Description
This book investigates the architecture design, physical implementation, result evaluation, and feature analysis of a many-core processor for DSP applications. The system is composed of a 2-D array of simple single-issue programmable processors interconnected by a reconfigurable mesh network, and processors operate completely asynchronously with respect to each other in a Globally Asynchronous Locally Synchronous fashion. The processor is called Asynchronous Array of simple Processors (AsAP). A 6Ã6 array has been fabricated in a 0.18 µm CMOS technology. The physical design concerns timing issues for robust implementations, and takes full advantages of their potential scalability. Each processor occupies 0.66 mm², is fully functional at a clock rate of 520-540 MHz under 1.8 V, and dissipates 94 mW while the clock is 100% active. The system is also easily scalable, and is well- suited to future fabrication technologies.
EXTRA 10 % discount with code: EXTRA
The promotion ends in 19d.18:08:16
The discount code is valid when purchasing from 10 €. Discounts do not stack.
- Author: Zhiyi Yu
- Publisher: VDM Verlag
- ISBN-10: 3639098595
- ISBN-13: 9783639098594
- Format: 15.2 x 22.9 x 0.9 cm, softcover
- Language: English English
This book investigates the architecture design, physical implementation, result evaluation, and feature analysis of a many-core processor for DSP applications. The system is composed of a 2-D array of simple single-issue programmable processors interconnected by a reconfigurable mesh network, and processors operate completely asynchronously with respect to each other in a Globally Asynchronous Locally Synchronous fashion. The processor is called Asynchronous Array of simple Processors (AsAP). A 6Ã6 array has been fabricated in a 0.18 µm CMOS technology. The physical design concerns timing issues for robust implementations, and takes full advantages of their potential scalability. Each processor occupies 0.66 mm², is fully functional at a clock rate of 520-540 MHz under 1.8 V, and dissipates 94 mW while the clock is 100% active. The system is also easily scalable, and is well- suited to future fabrication technologies.
Reviews