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High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip
High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip
229,58
255,09 €
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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in…
255.09
  • Publisher:
  • Year: 2017
  • ISBN-10: 9811010722
  • ISBN-13: 9789811010729
  • Format: 15.6 x 23.4 x 1.4 cm, kieti viršeliai
  • Language: English
  • SAVE -10% with code: EXTRA

High-Level Estimation and Exploration of Reliability for Multi-Processor System-On-Chip (e-book) (used book) | bookbook.eu

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This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

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  • Author: Zheng Wang
  • Publisher:
  • Year: 2017
  • ISBN-10: 9811010722
  • ISBN-13: 9789811010729
  • Format: 15.6 x 23.4 x 1.4 cm, kieti viršeliai
  • Language: English English

This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.

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