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- Author: Brandon Noia
- Publisher: Springer
- Year: 2013
- Pages: 245
- ISBN-10: 3319023772
- ISBN-13: 9783319023779
- Format: 15.2 x 23.4 x 2 cm, hardcover
- Language: English
- SAVE -10% with code: EXTRA
Design-For-Test and Test Optimization Techniques for Tsv-Based 3D Stacked ICS (e-book) (used book) | bookbook.eu
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Description
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
EXTRA 10 % discount with code: EXTRA
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- Author: Brandon Noia
- Publisher: Springer
- Year: 2013
- Pages: 245
- ISBN-10: 3319023772
- ISBN-13: 9783319023779
- Format: 15.2 x 23.4 x 2 cm, hardcover
- Language: English English
This book describes innovative techniques to address the testing needs of 3D stacked integrated circuits (ICs) that utilize through-silicon-vias (TSVs) as vertical interconnects. The authors identify the key challenges facing 3D IC testing and present results that have emerged from cutting-edge research in this domain. Coverage includes topics ranging from die-level wrappers, self-test circuits, and TSV probing to test-architecture design, test scheduling, and optimization. Readers will benefit from an in-depth look at test-technology solutions that are needed to make 3D ICs a reality and commercially viable.
Reviews