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- Author: Ricardo Martins
- Publisher: Springer
- ISBN-10: 3319816683
- ISBN-13: 9783319816685
- Format: 15.6 x 23.4 x 1.2 cm, minkšti viršeliai
- Language: English
- SAVE -10% with code: EXTRA
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Description
This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.
EXTRA 10 % discount with code: EXTRA
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- Author: Ricardo Martins
- Publisher: Springer
- ISBN-10: 3319816683
- ISBN-13: 9783319816685
- Format: 15.6 x 23.4 x 1.2 cm, minkšti viršeliai
- Language: English English
This book introduces readers to a variety of tools for analog layout design automation. After discussing the placement and routing problem in electronic design automation (EDA), the authors overview a variety of automatic layout generation tools, as well as the most recent advances in analog layout-aware circuit sizing. The discussion includes different methods for automatic placement (a template-based Placer and an optimization-based Placer), a fully-automatic Router and an empirical-based Parasitic Extractor. The concepts and algorithms of all the modules are thoroughly described, enabling readers to reproduce the methodologies, improve the quality of their designs, or use them as starting point for a new tool. All the methods described are applied to practical examples for a 130nm design process, as well as placement and routing benchmark sets.
Reviews