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- Author: Bruce W Hunt
- Publisher: BiblioScholar
- ISBN-10: 1249584248
- ISBN-13: 9781249584247
- Format: 18.9 x 24.6 x 0.7 cm, softcover
- Language: English
- SAVE -10% with code: EXTRA
A Single Chip Low Power Implementation of an Asynchronous FFT Algorithm for Space Applications (e-book) (used book) | bookbook.eu
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Description
A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed bya discussion of circuit design parameters; specifically, those relevant to space applications. The generic architecture is explained with a survey of the 16-point FFT architecture specific to this project. An implementation, which included a test chip fabricated through MOSIS, is described. Finally, simulation results based on layout extractions are presented and an outline for future work is given.
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- Author: Bruce W Hunt
- Publisher: BiblioScholar
- ISBN-10: 1249584248
- ISBN-13: 9781249584247
- Format: 18.9 x 24.6 x 0.7 cm, softcover
- Language: English English
A fully asynchronous fixed point FFT processor is introduced for low power space applications. The architecture is based on an algorithm developed by Suter and Stevens specifically for a low power implementation. The novelty of this architecture lies in its high localization of components and pipelining with no need to share a global memory. High throughput is attained using large numbers of small, local components working in parallel. A derivation of the algorithm from the discrete Fourier transform is presented followed bya discussion of circuit design parameters; specifically, those relevant to space applications. The generic architecture is explained with a survey of the 16-point FFT architecture specific to this project. An implementation, which included a test chip fabricated through MOSIS, is described. Finally, simulation results based on layout extractions are presented and an outline for future work is given.
Reviews